The present invention relates to a device simulator for analyzing an operation of a semiconductor device and, more particularly, to a device simulator for two-dimensionally analyzing a three dimensional device structure.
FIGS. 5 and 6 are block diagrams showing first and second examples of a conventional device simulator, in which FIG. 5 shows a decouple method, and FIG. 6 shows a couple method. (Ryo Dan ed., "Process Device Simulation Technique," pp. 4 to 9, Sangyo Tosho).
The first conventional example of FIG. 5 comprises a data input means 10, a simulating means 20c, a data output means 40, and an auxiliary storage unit 50. The simulating means 20c includes a potential setting means 21, a Poisson's equation solving means 23, an electron current continuity solving means 24, a hole current continuity solving means 25, and a result confirming means 28. For semiconductor fundamental equation data supplied by the data input means 10, the simulating means 20c applies a potential to electrodes by using the potential setting means 21 and sequentially solves a Poisson's equation, an electron current continuity, and a hole current continuity for an entire region except for the electrodes by using the respective solving means 23 to 25 while checking the convergences. After the result confirming means 28 confirms the result, the data output means 40 outputs the result.
The second conventional example of FIG. 6 comprises, in place of the solving means 23, 24, and 25 shown in FIG. 5, a Poisson's equation current continuity solving means 29 as a simulating means 20d. This second conventional example solves a Poisson's equation, an electron current continuity, and a hole current continuity in a batch manner and checks the convergence.
Note that as the solution of a semiconductor fundamental equation data described above, a solution using a numerical analysis such as calculus of finite differences has been established in the case of a two dimensional model.
A conventional analysis scheme for analyzing a charge coupled, device (referred to as a CCD hereinafter) as a three dimensional structure by using a tow dimensional device simulator will be described below. In a CCD 60 as shown in FIG. 7, carriers produced by light incident on a photodiode portion 61 are transferred to a vertical CCD portion 63 by a potential applied to a transfer gate portion 62. The carriers transferred to the vertical CCD portion 63 are transferred to the direction of depth (the direction perpendicular to the drawing surface of FIG. 7) of the CCD 60 by a potential difference applied in the direction of depth of the CCD 60. In the conventional analysis scheme, in order to analyze a potential distribution below the transfer gate, dummy electrodes are provided in the vertical CCD portion 63. A voltage is applied to the dummy electrodes until a region including the dummy electrodes is depleted sufficiently, thereby performing a simulation. Thereafter, another simulation is performed again after the dummy electrodes are removed, thus checking the physical quantity distribution inside the semiconductor. (Kawazoe et al., Application of 2D Device Simulator to Development of CCD Image Sensor, 1990, spring, the 37th Applied Physics Association Joint Lecture Meeting Manuscripts, the 0th Separate Volume, page 1,208; and Kitamura et al., Sensitivity Simulation of a Frame Transfer CCD Image Sensor, 1990, spring, the 37th Applied Physics Association Joint Lecture Meeting Manuscripts, the 2nd Separate Volume, page 629.)
In the conventional 2D device simulation system of Kawazoe or Kitamura, in order to check the physical quantity inside a device, dummy electrodes which provide as a carrier transfer portion to the vertical CCD portion are detached in order to perform the simulation. Therefore, since no place is present to absorb carriers transferred from the photodiode portion to the vertical CCD portion, no current can flow. As a result, it is impossible to analyze the manner in which carriers produced in the photodiode portion are transferred to the vertical CCD portion.